1. Field of the Invention
The present invention relates to a data processing device including a plurality of microprocessor units (hereinafter referred to as "MPUs") and a dual port memory device having a plurality of ports for carrying out data reading (writing).
2. Description of the Related Art
The above data processing device generally operates as follows.
For example, two MPUs access the memory device in an asynchronous manner so that, for example, one MPU performs an access for reading data present at an address (memory cell) within the memory device and the remaining MPU performs an access for writing data at another address (memory cell) within the memory device.
The effect of the above accessing is that data at an address (memory cell) present in the memory device is read-out and externally provided data is written to the other address (memory cell) within the memory device.
However, the case where a single address within the memory device is accessed by the two MPUs at the same time has to be considered because the above accesses to the memory device are carried out in an asynchronous manner. When one of these accesses (one MPU access) is a read operation and the other access (other MPU access) is a write operation, there is the undesirable possibility that the data being, read may be changed as a result of the data being, written.
Improvements are therefore desired when a plurality of MPUs access a single address within the memory device.